Tegola Structure Optimizer™
Custom Results - Without the Added Resources or Schedule Delay
Key Benefits
- Close on Timing, Power, and Area Simultaneously
- Reduce Overall Wire Loads with Cell Compaction
- Speed up Paths, Lower Power using low/high VT Cell Swapping
- Perform Quick What-If Cell Sizing Decisions Using Tegola's internal timer
Overview
As process nodes have advanced to smaller transistor geometries, the interconnect load has not scaled down as fast. Designers are well aware that what is already happening with 130 nm, 90 nm processes, and beyond, is smaller transistors are driving larger wire loads. This forces synthesis, optimization, and place & route tools to increase cell drive strengths, insert repeaters, increase power, and deal with signals more susceptible to signal integrity issues.
Structured or datapath placement does not reverse this physical trend, but it has emerged as a rapidly growing option for high performance designers. It is a way for engineers to eliminate as much of the overall wire loads as possible. In many cases, design objectives for performance and power are met that are either too intractable or time consuming to achieve by other means.
Solution
Tegola Structure Optimizer™ offers designers easy access to an advanced design methodology, referred to as structured placement. Structured design delivers many of the benefits of full-custom design, at a fraction of the cost.
As with full-custom design, objectives may include aggressive design frequency, ultra low power consumption, and area reduction. Tegola’s key contribution to engineering is that with modern libraries, the majority of benefits of full-custom circuits can be realized just by using the tool to lay out an intelligent physical structure. In the Tegola environment, designers work solely with gate level libraries and do not invest in custom transistor sizing or circuit level simulation.
Structured placement, tiled, bit-slice or datapath design does not add additional resources or threaten schedule delays. Indeed, schedules become more predictable by having explicit control over physical design.
Tegola enables engineers to deliver predictable behavior in terms of timing, power, and area. As might be expected, functions with inherent logical structure are prime candidates for structured design. For example, Tegola may offer the best approach in the data path portion of a design, where regular and/or repetitive logic structures exist. Indeed, in many cases, these functions are the focal points for overall chip performance. On the other hand, conventional synthesis and place & route tools may still be best to handle control logic.
Surprising Gains - Compounded Productivity
Designers tell us that having control over placement throughout the entire design flow enables an augmenting cycle where design speed, power, and area can all converge simultaneously to respective minimums.
Compacting or tiling cells next each other reduces wire length between logically connected cells. Capacitive and resistive loads, and hence parasitic charge and voltage drop are reduced. This enables the tool to select lower drive strength cells. These cells tend to be faster and smaller. Lower drive cells have reduced leakage and switching current, lowering static and dynamic power consumption. The smaller drive cells and reduced wiring reduce overall area. With cells placed next to each other in an orderly structure, the placement substantially simplifies routing.
Even more, reduced wire lengths for a datapath or structured design can mitigate risks by alleviating cross coupling between signals. Especially since datapath blocks usually come in bus groups (i.e. 16, 32, or 64 bits...), having bit sliced tiled cells reduces the need for buffering cross-talk violations later in the flow.
Logical design structure can be surprisingly easy for engineers to comprehend. With powerful analytical tools, visualization, and automated support at their fingertips, structured design makes it feasible and cost effective for good engineers to figure out how to meet very aggressive goals.