Stelvio Tapeout Accelerator™
Directed Optimization - Ready for Design Closure
Key Benefits
- Predictable Tapeouts - On Time, On Budget, Every Time
- High Performance - Finish Timing Closure Faster
- Ultra High Capacity - Close Timing at the Top Level
- Direct Control - Fix Timing Violations, the First Time
Visualize, analyze, optimize and manage all your ECO (Engineering Change Orders) in one place. Stelvio helps you better analyze and optimize timing to ensure your design tape-outs are delivered on schedule.
Stelvio is designed to fix late stage timing violations as they occur during the physical design process from within your existing design flow and save time by not having to repeat previous steps. Unforeseen timing violations may occur after placement, routing, metal fill and/or post silicon. Stelvio is the ultimate ECO compiler to analyze and close timing with surgical control at the top-level of a completely flat design database.
With Stelvio's high capacity, designers no longer have to deal with creating and reading abstraction models. Stelvio has been used to load a 40 million placed-instance design using only 32GB of memory.
We call it “predictable design optimization” because it enables you to:
- Work on the complete native design data without requiring any divide and conquer or abstraction methods that may inject timing inaccuracies.
- Utilize your golden reference STA (static timing analysis) tool within Stelvio to analyze and fix setup and hold time violations thus ensuring consistent static timing analysis through the design flow.
- Visualize your layout and make intelligent cell optimization decisions without impacting the surrounding area.
Stelvio provides you a methodology that combines consistent timing analysis and optimization tools with the right blend of usability and maximum flexibility, to manage ECOs to meet agressive chip delivery schedules.
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