Tego Design Accelerator
[sounds like "Leg-o"]

Some of our customers have told us that Structured Design techniques provided them with a 3x performance gain over synthesized results. This is an extraordinary result, and like dieting commercials, your results may vary. More realistically, our customers tell us they are able to get 30% or more gains in power, performance or area as a result of using structured techniques.

So why isn't everyone doing this? Because structured design requires thinking deeply about your design and the implementation. Most tools that structured designers use make it very difficult for them to run lots of rapid experiments, preventing the learning needed to make their design succeed.

It was this latter problem that Tuscany sought to solve with Tego. We wanted to build a tool that would allow the designer to quickly experiment with various structures and analyze the results all within the same design tool.

Imagine trying to put together a jigsaw puzzle, but instead of picking up pieces and trying to see if they fit and then putting them back, you had to look at all of the pieces and then write down each of the pieces number on a grid, run it through a machine that would arrange them based on your numbering and show you the result. You would probably get a few of them correct, but if you realized a whole section of the puzzle needed to move over to the other side, it requires a lot of work to do the renumbering.

Most structured design tools require designers to create some preliminary groups in a text or TCL file. They then have to run some extensive process to do the placement and see what the result is. When the result is bad and the designer decides they want to try something new, it requires completely rehacking the file and trying again. If every experiment takes you 30-60 minutes or more of hard but mundane mental activity, how many times would you try to find a better solution?

Most structured designers either give up trying to improve and just live with sub-optimal results because it is simply too difficult to make changes or to try alternate solutions.

Tego's goal is instead to provide a visual representation of the structure, along with graphical editing tools to allow you to manipulate the structure and quickly analyze experiments you are running. If you try something that isn't working, you can undo and take you to the previous result. Tego allows you to analyze wire length, timing, and power all within the same environment, changing the iterations from 30-60 minutes into seconds.

Moreover, Tuscany's structure language allows you to port IP to new process nodes while still maintaining the structure. This allows you to build up reusable Physical IP. In fact, one of our customers is leveraging Tego's ability to build module generators to maximum benefit. This provides the ultimate in reusability as a new specification for the DSP IP can be quickly reconfigured into a new fully laid out and optimally placed representation. This allows a greater degree of micro-architectural exploration.

Another one of our customers uses this extensively for quickly recreating Latch Based memory components. Due to Tego's ability to port between process nodes, they can quickly reconfigure new latch based memories to new nodes as well as quickly generate new versions in the same node. Since these memories are simply treated as pre-placed instances in the physical design flow (no hard macros required), Tego provides a significant value add to their design flow and efficiency.

If you're looking for a way to speed up your structured design, Contact Us for a live demo!